How does NAND gate work? (Very basic question)Why doesn't current flow through the common part of a...

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How does NAND gate work? (Very basic question)


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}







1












$begingroup$


I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.



Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.



I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?



The intuition I'm using (which may be totally wrong) is this:




  • Current acts like water gushing from V+ down all available paths.

  • At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.

  • The boolean equivalent of a 1 is that current is flowing through a point.


Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.



schematic diagram










share|improve this question









New contributor




rampatowl is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
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$endgroup$












  • $begingroup$
    The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
    $endgroup$
    – Sunnyskyguy EE75
    3 hours ago




















1












$begingroup$


I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.



Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.



I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?



The intuition I'm using (which may be totally wrong) is this:




  • Current acts like water gushing from V+ down all available paths.

  • At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.

  • The boolean equivalent of a 1 is that current is flowing through a point.


Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.



schematic diagram










share|improve this question









New contributor




rampatowl is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.







$endgroup$












  • $begingroup$
    The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
    $endgroup$
    – Sunnyskyguy EE75
    3 hours ago
















1












1








1





$begingroup$


I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.



Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.



I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?



The intuition I'm using (which may be totally wrong) is this:




  • Current acts like water gushing from V+ down all available paths.

  • At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.

  • The boolean equivalent of a 1 is that current is flowing through a point.


Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.



schematic diagram










share|improve this question









New contributor




rampatowl is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.







$endgroup$




I'll preface this question by saying that I am a software developer just starting to learn the basics of electronics, so it's very likely I'm missing some fundamental intuition here.



Below is a mechanical NAND gate with two switches. I think it's supposed to be obvious that when the switches are closed, the output Q is 0 rather than 1. I don't see why this is.



I see that when the two switches are closed, there is a path from V+ to ground, and that current will flow to ground. But there's also a path from V+ to Q, so won't some current still flow to the output, putting it in a 1 state?



The intuition I'm using (which may be totally wrong) is this:




  • Current acts like water gushing from V+ down all available paths.

  • At a junction, current will flow through both paths in an amount inversely proportional to resistance. In this case, both paths have no additional resistance so they should split the current equally.

  • The boolean equivalent of a 1 is that current is flowing through a point.


Please help me understand what I'm missing! And if you can point me to a book or online resource explaining these fundamentals, that would be very helpful. I've tried looking at a lot of "circuit tutorial" content on Google, but surprisingly haven't been able to resolve my confusion here.



schematic diagram







circuit-analysis logic-gates






share|improve this question









New contributor




rampatowl is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.











share|improve this question









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share|improve this question




share|improve this question








edited 3 hours ago









SamGibson

11.8k41739




11.8k41739






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asked 3 hours ago









rampatowlrampatowl

1083




1083




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New contributor





rampatowl is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
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Check out our Code of Conduct.












  • $begingroup$
    The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
    $endgroup$
    – Sunnyskyguy EE75
    3 hours ago




















  • $begingroup$
    The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
    $endgroup$
    – Sunnyskyguy EE75
    3 hours ago


















$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
3 hours ago






$begingroup$
The source impedance of the switch is 0 while in normal logic it is <=50 Ohms so the load impedance being much higher permits many loads to applied without significant change in voltage. For TTL, the limit was 10 units of load. But for static CMOS , the limit depends on the equivalent input capacitance and current limit of the switch as this affects rise/fall time. T=RC
$endgroup$
– Sunnyskyguy EE75
3 hours ago












4 Answers
4






active

oldest

votes


















4












$begingroup$


The boolean equivalent of a 1 is that current is flowing through a point.




That's the fundamental confusion leading to difficulty in understanding the circuit.



Single ended logic like this encodes state as voltage not current.



Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.



Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.






share|improve this answer











$endgroup$













  • $begingroup$
    Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
    $endgroup$
    – rampatowl
    3 hours ago










  • $begingroup$
    Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
    $endgroup$
    – Chris Stratton
    3 hours ago










  • $begingroup$
    Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
    $endgroup$
    – rampatowl
    2 hours ago






  • 1




    $begingroup$
    Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
    $endgroup$
    – Chris Stratton
    2 hours ago










  • $begingroup$
    Thanks, I appreciate the help!
    $endgroup$
    – rampatowl
    2 hours ago



















1












$begingroup$

I also had this problem since I started learning a bit about electronics (I'm also a software engineer).



Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).



This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).



However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.






share|improve this answer









$endgroup$





















    1












    $begingroup$

    First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense





    schematic





    simulate this circuit – Schematic created using CircuitLab



    You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.






    share|improve this answer










    New contributor




    vaporlock is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
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    $endgroup$





















      0












      $begingroup$

      I found very useful the simple description of a NAND gate to act thusly
      "any zero in causes a one out".



      This circuit will do that





      schematic





      simulate this circuit – Schematic created using CircuitLab






      share|improve this answer









      $endgroup$













      • $begingroup$
        Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
        $endgroup$
        – Ben Voigt
        1 hour ago












      Your Answer






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      4 Answers
      4






      active

      oldest

      votes








      4 Answers
      4






      active

      oldest

      votes









      active

      oldest

      votes






      active

      oldest

      votes









      4












      $begingroup$


      The boolean equivalent of a 1 is that current is flowing through a point.




      That's the fundamental confusion leading to difficulty in understanding the circuit.



      Single ended logic like this encodes state as voltage not current.



      Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.



      Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.






      share|improve this answer











      $endgroup$













      • $begingroup$
        Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
        $endgroup$
        – rampatowl
        3 hours ago










      • $begingroup$
        Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
        $endgroup$
        – Chris Stratton
        3 hours ago










      • $begingroup$
        Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
        $endgroup$
        – rampatowl
        2 hours ago






      • 1




        $begingroup$
        Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
        $endgroup$
        – Chris Stratton
        2 hours ago










      • $begingroup$
        Thanks, I appreciate the help!
        $endgroup$
        – rampatowl
        2 hours ago
















      4












      $begingroup$


      The boolean equivalent of a 1 is that current is flowing through a point.




      That's the fundamental confusion leading to difficulty in understanding the circuit.



      Single ended logic like this encodes state as voltage not current.



      Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.



      Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.






      share|improve this answer











      $endgroup$













      • $begingroup$
        Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
        $endgroup$
        – rampatowl
        3 hours ago










      • $begingroup$
        Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
        $endgroup$
        – Chris Stratton
        3 hours ago










      • $begingroup$
        Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
        $endgroup$
        – rampatowl
        2 hours ago






      • 1




        $begingroup$
        Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
        $endgroup$
        – Chris Stratton
        2 hours ago










      • $begingroup$
        Thanks, I appreciate the help!
        $endgroup$
        – rampatowl
        2 hours ago














      4












      4








      4





      $begingroup$


      The boolean equivalent of a 1 is that current is flowing through a point.




      That's the fundamental confusion leading to difficulty in understanding the circuit.



      Single ended logic like this encodes state as voltage not current.



      Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.



      Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.






      share|improve this answer











      $endgroup$




      The boolean equivalent of a 1 is that current is flowing through a point.




      That's the fundamental confusion leading to difficulty in understanding the circuit.



      Single ended logic like this encodes state as voltage not current.



      Inputs of logic gates are designed to source or sink very little current, so the output of the previous stage is easily able to impose its intended voltage on the connection between output and the following input with very little current needing to flow.



      Current-mode signaling does exist, but it's generally used only in noisy situations, for example the time-tested 4-20 mA current loop standard.







      share|improve this answer














      share|improve this answer



      share|improve this answer








      edited 3 hours ago

























      answered 3 hours ago









      Chris StrattonChris Stratton

      23.8k22867




      23.8k22867












      • $begingroup$
        Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
        $endgroup$
        – rampatowl
        3 hours ago










      • $begingroup$
        Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
        $endgroup$
        – Chris Stratton
        3 hours ago










      • $begingroup$
        Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
        $endgroup$
        – rampatowl
        2 hours ago






      • 1




        $begingroup$
        Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
        $endgroup$
        – Chris Stratton
        2 hours ago










      • $begingroup$
        Thanks, I appreciate the help!
        $endgroup$
        – rampatowl
        2 hours ago


















      • $begingroup$
        Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
        $endgroup$
        – rampatowl
        3 hours ago










      • $begingroup$
        Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
        $endgroup$
        – Chris Stratton
        3 hours ago










      • $begingroup$
        Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
        $endgroup$
        – rampatowl
        2 hours ago






      • 1




        $begingroup$
        Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
        $endgroup$
        – Chris Stratton
        2 hours ago










      • $begingroup$
        Thanks, I appreciate the help!
        $endgroup$
        – rampatowl
        2 hours ago
















      $begingroup$
      Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
      $endgroup$
      – rampatowl
      3 hours ago




      $begingroup$
      Gotcha. Can you explain why the voltage of Q is only positive when there is no path from V+ to ground?
      $endgroup$
      – rampatowl
      3 hours ago












      $begingroup$
      Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
      $endgroup$
      – Chris Stratton
      3 hours ago




      $begingroup$
      Because in a "tug of war" the low resistance switches win over the pulling resistor in imposing the voltage on their far side.
      $endgroup$
      – Chris Stratton
      3 hours ago












      $begingroup$
      Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
      $endgroup$
      – rampatowl
      2 hours ago




      $begingroup$
      Oh of course! So is the rule something like: to determine whether an input pin is high or low, look at every defined component it is connected to, and it will take on the value of the defined component with the least resistance along the path to that component?
      $endgroup$
      – rampatowl
      2 hours ago




      1




      1




      $begingroup$
      Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
      $endgroup$
      – Chris Stratton
      2 hours ago




      $begingroup$
      Approximately: but not just the components but what is behind them, in this case "stiff" voltage rails. And if the difference in resistances is not drastic then the voltage may end up intermediate.
      $endgroup$
      – Chris Stratton
      2 hours ago












      $begingroup$
      Thanks, I appreciate the help!
      $endgroup$
      – rampatowl
      2 hours ago




      $begingroup$
      Thanks, I appreciate the help!
      $endgroup$
      – rampatowl
      2 hours ago













      1












      $begingroup$

      I also had this problem since I started learning a bit about electronics (I'm also a software engineer).



      Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).



      This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).



      However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.






      share|improve this answer









      $endgroup$


















        1












        $begingroup$

        I also had this problem since I started learning a bit about electronics (I'm also a software engineer).



        Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).



        This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).



        However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.






        share|improve this answer









        $endgroup$
















          1












          1








          1





          $begingroup$

          I also had this problem since I started learning a bit about electronics (I'm also a software engineer).



          Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).



          This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).



          However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.






          share|improve this answer









          $endgroup$



          I also had this problem since I started learning a bit about electronics (I'm also a software engineer).



          Electricity always wants to balance. If there is GND, all electricity will flow to there (actually the electrons move in reverse direction but let's ignore that for now).



          This means if the switches are closed, and if Q > 0 V, all electricity will flow to GND, meaning Q will be 0 V in a very short time (read: almost instantly).



          However, when one of the switches is open, the voltage from V+ will flow to Q if Q has less voltage than V+ (which is likely so), so Q will end up having the same voltage as V+.







          share|improve this answer












          share|improve this answer



          share|improve this answer










          answered 3 hours ago









          Michel KeijzersMichel Keijzers

          7,26093373




          7,26093373























              1












              $begingroup$

              First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense





              schematic





              simulate this circuit – Schematic created using CircuitLab



              You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.






              share|improve this answer










              New contributor




              vaporlock is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
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              $endgroup$


















                1












                $begingroup$

                First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense





                schematic





                simulate this circuit – Schematic created using CircuitLab



                You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.






                share|improve this answer










                New contributor




                vaporlock is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                Check out our Code of Conduct.






                $endgroup$
















                  1












                  1








                  1





                  $begingroup$

                  First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense





                  schematic





                  simulate this circuit – Schematic created using CircuitLab



                  You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.






                  share|improve this answer










                  New contributor




                  vaporlock is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                  Check out our Code of Conduct.






                  $endgroup$



                  First off the "N" means that it inverts the input the schematic is sort of doing the same but it gets off track of how the gates work. If you drew it with a relay it would make more sense





                  schematic





                  simulate this circuit – Schematic created using CircuitLab



                  You need to study pull down and pull up resistors, the value of the resistor limits the voltage, current is not an issue really because this is all at "logic level". I had a hard time with the logic stuff at first and then all of a sudden it all made sense, good luck my friend.







                  share|improve this answer










                  New contributor




                  vaporlock is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                  Check out our Code of Conduct.









                  share|improve this answer



                  share|improve this answer








                  edited 2 hours ago





















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                  answered 3 hours ago









                  vaporlockvaporlock

                  113




                  113




                  New contributor




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                  New contributor





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                      0












                      $begingroup$

                      I found very useful the simple description of a NAND gate to act thusly
                      "any zero in causes a one out".



                      This circuit will do that





                      schematic





                      simulate this circuit – Schematic created using CircuitLab






                      share|improve this answer









                      $endgroup$













                      • $begingroup$
                        Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                        $endgroup$
                        – Ben Voigt
                        1 hour ago
















                      0












                      $begingroup$

                      I found very useful the simple description of a NAND gate to act thusly
                      "any zero in causes a one out".



                      This circuit will do that





                      schematic





                      simulate this circuit – Schematic created using CircuitLab






                      share|improve this answer









                      $endgroup$













                      • $begingroup$
                        Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                        $endgroup$
                        – Ben Voigt
                        1 hour ago














                      0












                      0








                      0





                      $begingroup$

                      I found very useful the simple description of a NAND gate to act thusly
                      "any zero in causes a one out".



                      This circuit will do that





                      schematic





                      simulate this circuit – Schematic created using CircuitLab






                      share|improve this answer









                      $endgroup$



                      I found very useful the simple description of a NAND gate to act thusly
                      "any zero in causes a one out".



                      This circuit will do that





                      schematic





                      simulate this circuit – Schematic created using CircuitLab







                      share|improve this answer












                      share|improve this answer



                      share|improve this answer










                      answered 2 hours ago









                      analogsystemsrfanalogsystemsrf

                      16.6k2823




                      16.6k2823












                      • $begingroup$
                        Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                        $endgroup$
                        – Ben Voigt
                        1 hour ago


















                      • $begingroup$
                        Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                        $endgroup$
                        – Ben Voigt
                        1 hour ago
















                      $begingroup$
                      Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                      $endgroup$
                      – Ben Voigt
                      1 hour ago




                      $begingroup$
                      Looks like an 'OR' gate to me... but maybe I just don't understand how you intend for those switches to work (that's a problem with your answer -- you didn't even try to describe their behavior)
                      $endgroup$
                      – Ben Voigt
                      1 hour ago










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